SystemVerilog for Verification Part 2 : Projects
Verification of Common Peripherals, Memories, and Bus Protocol.Wat je leert: Verification of Memories viz. FIFO , Verification of Bus Protocols viz. APB, AHB, AXI, Whishbone , Verification of Interface Communication Protocols viz. SPI, UART..
Doelgroep: Alle niveaus..
Duur:
12 uur in totaal
Taal: Engels